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SH3001 microbudd y? real - time clock and clock management support ic for microcontrollers system management 2003 - 08 - 08 copyright ?2002 - 2005 sem tech corporation 1 SH3001 data sheet v1.15 www.semtech.com description the programmable SH3001 microbuddy? (buddy?) provides mandatory microcontroller support functions: clock management system real - time support auxiliary functions three components make a complete system: any microcontroller, the SH3001, and a by pass capacitor. this low - cost system would consume very little power and have clock - frequency accuracy of 0.5%. a fourth component, a 32.768 khz crystal, raises the clock frequency accuracy to 0.0256% ( 256 ppm). the SH3001 can operate completely st and - alone, or under control of the microcontroller. a single - wire interface handles bi - directional communications. the SH3001 stores all configuration, calibration, parameters, and status information in a 36 - byte bank of control registers. on reset, mos t of these are reloaded with defaults from the factory - set nonvolatile memory. the microcontroller can change any settings on the fly. if some of the settings must remain fixed, a comprehensive set of write - protect bits is provided for several related gr oups of registers (with both permanent write - inhibit and lock/unlock capabilities). a backup power source can also be connected to the SH3001 . the ic can directly accommodate 2/3 - cell zinc - carbon/alkaline, 2/3 - cell mercury, 2/3/4 - cell nicd/nimh, 1 - cell li /li+ batteries, or a super cap. applications home automation and security consumer products portable/handheld computers industrial equipment any microcontroller - based product features highly integrated ic - 3 mm x 3 mm x 0.9 mm 16 - lead mlp (qfn ) package clock management system - replaces high - frequency (hf) crystal or resonator - programmable clock output from 32.768 khz to 16 mhz - speed shift between multiple clock frequencies - adjustable spectrum spreading for emi reduction - directly suppor ts microcontroller stop function - deep sleep with instantaneous auto - wakeup real - time support - 179 - year real - time clock, battery - backup capable - dedicated 32.768 khz buffered clock output - built - in trim for 32.768 khz oscillator to 4 ppm - programma ble periodic interrupt / wakeup timer operates from 2.3 v to 5.5 v i dd <850 m a / 2 mhz, <3 ma / 16 mhz, <10 m a / standby i bup <2 m a / i bsb <50 na (battery backup / standby) pin configuration 3mm mlp (qfn) package SH3001 m b tm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 v ss v reg v dd v bak x in x out clk sel v ss nc nc t est (v ss ) nc clk32 io/i nt clk in clk out v+ typical application circuit with high clock accuracy SH3001 m b tm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 m c ontroller v dd x in x out gpio with int g nd c bypass covered by us patent no. 6,903,986 semtech, the semtech logo, microbuddy, buddy, and b are marks of semtech corporation. a ll other marks belong to their respective owners.
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 2 v1.15 www.semtech.co m description ordering information SH3001imltr ic mlp 3 x 3 mm, 16 pins, - 40 c to +85 c SH3001imltr t ic mlp 3 x 3 mm, 16 pins, - 40 c to +85 c, lead free evk - sh3000usb sh3000 evaluation kit sh3000ek.pdf sh3000 evaluation kit user guide sh3000um.pdf sh3000 reference manual block diagram clk32 microcontroller v+ v dd 32.768 k h z x in x out i/o pin clk sel v bak v reg lf oscillator hf oscillator & fll real - time clock periodic interrupt / wake - up timer x tal oscillator r egulators & battery back - up nonvolatile memory calibration & default settings serial i/o control logic 8 clock driver & start/stop logic post - scaler 2 3 4 12 5 6 7 13 14 15 16 interrupt v dd v ss x in x out voltage reference clk out clk in t est io/i nt SH3001 buddy? 1 v ss 10 11 9 t est nc nc nc
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 3 v1.15 www.semtech.co m pin descriptions pin name type function 1 v ss power ground, 0 v. all v ss pins and t est (v ss ) pin must be connected together. 2 v reg power output of internal voltage regulator, 2.2 v nominal. this pin can power external loads of <5 ma. if load is ?noisy? it requires a bypass capacitor. may be left unconnected or used as a high logic level signal for clk sel pin (see below). 3 v dd power main power supply, +2.3 to +5 .5 v. 4 v bak power backup power supply for real - time clock, +2.3 to +5.5 v (+1.8 to +5.5 v typical). this voltage can be higher or lower than v dd . connect a backup battery or backup capacitor (with external recharge circuit). connect to v dd if not used . 5 x in analog in 6 x out analog out oscillator pins for optional external low frequency crystal, typically 32.768 khz crystal with nominal 12.5 pf load capacitance. keep open or connect to v ss if not used. 7 clk sel digital in must be tied to v reg 8 v ss power ground, 0 v. all v ss pins and t est (v ss ) pin must be connected together. 9 nc not connected - reserved 10 nc not connected - reserved 11 nc not connected - reserved 12 t est (v ss ) digital in factory test enable. all v ss pins and t est (v ss ) pin must be connected together. 13 clk32 digital out buffered internal 32.768 khz clock, derived according to the clk sel pin setting. this pin uses backup power for the buffer when v dd is not present. when driving high, this signal is either at v bak or v dd (if v dd is higher than the reset threshold). when enabled, this signal runs continuously independent of clk out activity. minimize the external load to reduce power consumption during backup operations. when disabled, this pin is driven to v ss . kee p open if not used. 14 io/i nt i/o serial communications interface and interrupt output pin. this pin is internally weakly pulled to the opposite of the programmed interrupt polarity. for example, if interrupt is programmed to be active low, this pin is weakly pulled to v dd when inactive. keep open if not used. 15 clk in digital in clock activity sense input. used to detect when the target microcontroller enters stop mode (which disables its clock). connect to the microcontroller?s clock output or osci llator output pin. connect to v ss when not used . clk in must not be left open. 16 clk out digital out programmable high frequency clock output. connect to the target microcontroller?s clock input or oscillator input pin. keep open if not used.
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 4 v1.15 www.semtech.co m functi onal description the SH3001 is a single - chip support system for microcontrollers, microprocessors, dsps and asics. it consists of three major functional blocks, each block having numerous enhancements over alternative solutions. the major modules are the clock management system, the real - time support, and the auxiliary functions. the entire chip is controlled by the set of internal registers and accessed via the single - pin serial interface. all of the settings, configuration, and calibration or operating parameters are programmable and re - programmable at any time. all of the parameters required for stand - alone operations are initialized on reset from the built - in factory - programmed nonvolatile memory. this allows the SH3001 to operate autonomously for mo st of its supervisory functions. the stand - alone operations do not require the use of the serial interface or any of the initialization and control operation, but without these, the full potential benefit of the SH3001 might not be realized. in the prefer red configuration, where the SH3001 is tightly coupled to the target micro, the SH3001 offers an unprecedented level of design flexibility in clock and power usage management. the SH3001 is a particularly desirable integration because the built - in feature s interact and meld to produce more useful system level functions. the SH3001 offers several ways to minimize system power consumption, such as allowing the target processor to enter deep sleep by stopping its clock completely, and to wake up as often as n ecessary with no external support. the clock can be programmed to start up at a given frequency, and software can adjust it dynamically to manage power consumption and different operating modes. users should consider the interactions of the major function al blocks to gain the maximum advantage from the SH3001. the individual functional blocks are described in the following sections.
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 5 v1.15 www.semtech.co m clock management system the SH3001 provides a flexible tool for creating and managing clocks, a versatile and accurate ?any frequency? clock synthesizer (see figure 1 ). it is capable of generating any frequency in the range of 62.5 khz to 16.0 mhz, with worst - case resolution of 0.0256% (256 ppm). the internal 32.768 khz clock can also be routed to the clk out pin (and hf oscillator stopped for energy savings). the objectives, features, and behavior of the clock management system are aimed towards the systems that utilize a microcontroller, a microprocessor, a dsp or an asic. the SH3001 permits the automatic sensing of the intentions of the host processor, an industry first. the SH3001 shuts down its clock output when it senses that the host processor issued a stop instruction. subsequently, the SH3001 idles, consuming less than 10 a. as soon as the host exits the stop mode, the SH3001 instantaneously starts to supply a stable clock (<2s wake - up). a typical system, constructed with a ceramic resonator or a crystal as the frequency determining element, must wait at le ast several hundred microseconds (for a resonator), or as much as 100 ms or more (for a hf crystal), to re - start the oscillator. the SH3001 allows the response to and service of an event to finish with a speed previously unattainable for a simple micropro cessor. a system with a traditional clock approach can be as much as 100x ? 10,000x slower. clock generator operation the frequency synthesizer in the SH3001 is constructed from the 2:1 tunable 8.0 ? 16.0 mhz hf oscillator followed by a programmable ?powe r - of - two? post - divider (see figure 1 ). the clock source selector and the programmable post - scale divider allow instantaneous switching between the 32.768 khz internal clock and divided - down hf oscillator output. there is no settling or instability when th e switch occurs. this is a preferred method for clock control in computing systems, when the large ratio between high and low frequency of operations allows for correspondingly large and instantaneous savings in power consumption. post - scaler (divide by 1, 2, 4, 8, 16, 32, 64, 128) figure 1. simplified hf oscillator system 32.768 khz s tart /s top 16 15 clk out clk in clock buffer and glue logic hf digitally controlled oscillator 8 - 16 mhz 18 - bit dco code register clock on force dco on clock source 1 0 spectrum spreading controls frequency locked loop logic 13 - bit frequency set value ? 16 2048 hz 8 - bit pseudo - random noise generator fll on from / to serial i/o
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 6 v1.15 www.semtech.co m when the hf oscillator is operating alone, it can set the frequency of the clock on the clk out pin to 0.025%, and maintain it to 0.5% over temperature. this compares favorable with the typical 0.5% initial clock accuracy and 0.6% overall temperature stability of cerami c resonators. the SH3001 replaces the typical resonator, using less space and providing better performance and functionality. the hf oscillator can also be locked to the internal 32.768 khz signal. the absolute accuracy and stability of the hf clock depe nds on the quality of the 32.768 khz internally generated clock; the low - frequency (lf) oscillator system is described later in this document. when the real - time clock module of the SH3001 is used for high - accuracy timekeeping, an external 32.768 khz cryst al used as a reference for rtc provides excellent accuracy and stability for the clock management system. the SH3001 employs a frequency locked loop (fll) to synchronize the hf clock to the 32.768 khz reference. this architecture has several advantages over the common pll (phase locked loop) systems, including the ability to stop and re - start without frequency transients or instability, and with instant settling to a correct frequency. the conventional pll approach invariably includes a low - pass filter that requires a long settling time on re - start. the primary purpose of the fll is the maintenance of the correct frequency while the ambient temperature is changing. as the temperature drift of the hf oscillator is quite small, any corrective action from the fll system is also small and gradual, commensurate with the temperature variation. the fll system in the SH3001 is unconditionally stable. to set a new frequency for the fll, the host processor writes the 13 - bit frequency set value. the resulting out put frequency is calculated using simple formulas [1] and [2] (reference frequency is 32.768 khz): f osc = 2048 hz * (frequency set value + 1) [1] f out = f osc / (post - divider setting) [2] for example, a post - divider setting of ? 8 and the frequency set value of 4000 (0x0fa0) produce an output frequency of 1.024 mhz. programmable spectrum spreading most commercial electronic systems must pass regulatory tests in order to determine the degree of their electromagnetic interference (emi) affecting other electronic devices. in some cases compliance with the emi standards is costly and complicated. the SH3001 offers a technique for reducing the emi. it can be a part of the initial design strategy, or it can be applied in the prototy pe stage to fix problems identified during compliance testing. this feature of the SH3001 can greatly reduce the requirements for radiofrequency shielding, and permits the use of simple plastic casings in place of expensive rfi - coated or metal casings. th e SH3001 employs programmable spectrum spreading in order to reduce the rf emissions from the processor?s clock. there are five (5) possible settings; please see table 1 for operating and performance figures in the 8 ? 16 mhz range. spectrum spreading is cr eated by varying the frequency of the hf oscillator with a pseudo - random sequence (with a zero - average dc component). the maximum - length sequence (mls) 8 - bit random number generator, clocked by 32.768 khz, is used. only 4, 5, 6, or 7 bits of the generate d 8 - bit random number are used, according to the configuration setting. maximum fluctuations of the frequency depend on the selected frequency range and the position within the range. selecting the hf oscillator frequency to be near the high end of the ra nge limits the peak variations to 0.1%, 0.2%, 0.4%, or 0.8% (corresponding to the configuration setting). table 1. emi reduction with spectrum spreading setting en cfg1 cfg0 spreading bandwidth khz peak emi reduction (guaranteed) db peak emi reduction (measured) db 0 x x off 0 0 1 0 0 32 - 3 - 3 1 0 1 64 - 6 - 7 1 1 0 128 - 9 - 10 1 1 1 256 - 12 - 15
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 7 v1.15 www.semtech.co m special operating modes the SH3001 can operate stand - alone, without connections to the in and out terminals of the host?s oscillator. for ex ample, a bank of SH3001 chips can generate several different frequencies for simultaneous use in the system, all controlled by a single micro (and possibly sharing one 32.768 khz crystal by chaining the clk32 pin to x in pin on the next device). in this ca se the clk in pin should be connected to v ss . the clock output on the clk out pin is continuous; the correct operating mode is automatically recognized by the SH3001 . real - time support the SH3001 has two support modules that are specifically designed for v arious real time support functions. they are the real - time clock and the periodic interrupt / wakeup timer. both of these units as well as other functions of the SH3001 depend on the internal 32.768 khz clock for accuracy. with one external component (a 32.768 khz crystal), the SH3001 can provide a processor clock accuracy of 256 ppm ( 0.0256%) and the accuracy of the real - time system of 4 ppm ( 0.0004%). a microcontroller might not have a stop command. with the SH3001, this controller can do a ?simulated? stop by issuing an instruction to the SH3001 to stop the clock. this command is accepted only if the periodic interrupt / wakeup timer has started (otherwise, once the system is put to sleep, it would never wake up again). this mode of operat ions is only possible if the host processor is capable of correct operations with clock frequency down to zero, and keeps all of the internal ram alive while the clock is stopped. low frequency (lf) oscillator system this module provides the 32.768 khz clo ck to all internal circuits and to the dedicated output pin, clk32. if enabled, the clk32 output continues normal operations when v dd is absent and backup power is available. when the power is first applied to the SH3001, the rc oscillator takes over. it supplies the 32.768 khz clock for start - up and initialization. once the crystal has started and stabilized, the internal 32.768 khz clock switches to the very accurate crystal frequency; see figure 2 . 5 6 7 v reg rc oscillator 13 internal 32.768 khz clock x - tal stable? internal r ref 32.768 khz crystal 12.5 pf load capacitance figure 2. simplified lf oscillator system 1 clk32 x in x out clk sel 8 v ss v ss clk32 o n 4 - bit value 6 - bit value 4 - bit value lock / unlock logic lock logic i nternal r ref o n from / to serial i/o
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 8 v1.15 www.semtech.co m the crystal oscillator has the useful feature of adju stable load capacitors. it permits tuning of the circuit for initial tolerance of the crystal (often 20 ppm) as well as an adjustment for the required load capacitance (with possible variations from the pcb layout). while the oscillator was designed fo r a crystal with a nominal load capacitance of 12.5 pf, the circuit accommodates any value from ~7 pf to 22 pf (depending on parasitics of the layout). all of these corrections can be performed when the part is already installed on the pcb, in the actual circuit. the default value for load capacitance (12.5 pf) loaded on power - up from the factory - programmed nonvolatile memory can be re - programmed at any time (following a secure process of unlocking the load capacitance value register and immediately writin g a new setting), or it can be completely protected from any changes by a permanent write - protect flag. this adjustment can set the frequency of the crystal oscillator to within 4 ppm of the ideal value. as a reference, a typical 32.768 khz crystal chan ges its frequency 4 ppm for a 10c change in temperature. since the temperature characteristics of crystals are well known and stable, the host processor is free to implement an algorithm for temperature compensation of the crystal oscillator using the ad justable load capacitors, with resulting accuracy of 4 ppm over the entire temperature range. real - time clock using the 4 ppm, 32.768 khz clock from the lf oscillator, the real - time clock module keeps time with a maximum error as low as 2 minutes pe r year. this compares favorably with a conventional error of 2 minutes per month for typical rtc chips. the hardware of the real - time clock is capable of 179 - years of calendar operations (see figure 3 ). all counting - chain values are loaded at the same tim e into corresponding registers when the fractions register is read. all values from registers are loaded into the counting - chain when the fractions register is written. the rtc continues normal operations when v dd is absent, if backup power is available. 14 figure 3. real time clock and periodic interrupt / wakeup timer io/i n t 16 - bit counter days (bin) 0 - 65535 256 hz 32 - bit time interval 32 - bit counter 32 - bit comparator 32 - bit latch interrupt logic serial i/o r eset ? 256 ? 60 ? 60 ? 24 1 hz lsb msb minutes (bcd) 0 - 59 seconds (bcd) 0 - 59 fractions (bin) 0 - 255 hours (bcd) 0 - 23 32 - bit latch l oad l oad lsb current timer value lsb msb 32.768 khz ? 128
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 9 v1.15 www.semtech.co m periodic interrupt / wakeup timer simple and versatile, the periodic interrupt / wakeup timer can be used to create very accurate recurring interrupts for use by the host micro. with some minimal software support from the host processor, it can also be used to create alarms, with practically unlimited duration. while the timer is running, the host processor can be halted, consuming no energy. the interrupt wakes up the processor, which can perform the requisite task and go back to sleep, until the next periodic interrupt. this mode of operation can achieve extremely low average power consumption. a 32 - bit counter clocked by 32.768 khz, producing a minimum interval of 30.5 s and the maximum interval of 36.4 hours, creates the timer. after reset, the time r is stopped until the new value for the time interval is written into the 4 - byte time interval register. when the least significant byte (lsb) is written, the whole value is moved to the time interval latch, the counter is reset and starts to increment w ith the 32.768 khz clock. when the 32 - bit comparator detects a match, an interrupt is generated and the counter is reset and starts the next timing cycle. although the counter cannot be written to, the current value from the counter can be read at any time . the whole 32 - bit value is loaded into the 32 - bit current timer value latch when the least significant byte is read. this prevents errors stemming from the finite time between the readings of individual bytes of the current value. auxiliary functions voltage regulator pin v reg can be used as a nominal 2.20 v reference voltage or a supply source for small loads (<2 ma). a bypass capacitor might be necessary between this pin and v ss , if the load generates large current transients or a low ripple refere nce is required.
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 10 v1.15 www.semtech.co m interrupt and serial interface a single line is used to convey bi - directional information between the SH3001 and the processor, and as the interrupt line to the processor. the polarity of the interrupt signal is programmable. the SH3001 and the host microcontroller communicate using a single wire, bi - directional asynchronous serial interface. the bit rate is automatically determined by the SH3001. . at the fastest possible rate, a read or write access of a single byte from the register bank takes 5 s. the SH3001 contains 36 addressable registers located at 0x00 ? 0x1f. some of these registers are accessed through a page operation. pin 14, io/int, is the serial communications interface and interrupt output pin. this pin is internally w eakly pulled to the opposite of the programmed interrupt polarity. for example, if interrupt is programmed to be active low, this pin is weakly pulled to v dd when inactive. as shown in figure 4 , the SH3001 and the host communicate with serial data streams . the host always initiates communication. a data stream consists of the following (in this order): 3 - bit start field 3 - bit read/write code 5 - bit address field 1 guard bit 8 - bit data field 2 parity bits plus, for write streams only: 1 guard bit 2 ackno wledge (ack) bits the 3 - bit start field (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream. the 3 - bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. this protec ts against early glitches that might otherwise put the interface into an invalid read or write access mode. the 5 - bit address field contains the address of the register. a single guard bit gives the interface a safe period in which to change data direction . the value of a guard bit does not matter. the 8 - bit data field is written to (read from) the register. two parity bits: the first parity bit is high when there are an odd number of bits in the read/write, address and data fields; the second parity bit i s the inverse of the first. for write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowledge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write acce ss. two guard bits are appended to the end of the access stream (read or write). the host can not start the next access before receiving these bits. the interface is self - timed based on the duration of the start bit field, and communication can take place whenever clk out is active, either at 32.768 khz or at a higher frequency. if the host microcontroller is running synchronously to the clk out generated by the SH3001 (which should generally be the case), then a minimum of 4 clk out cycles per bit are requi red to maintain communication integrity. if the host?s serial interface is asynchronous to clk out , then a minimum of 52 cycles per bit are necessary. a maximum of 1024 clk out cycles per bit field is supported. table 2 displays the minimum and maximum bit periods for the serial communications for clk out frequencies of 16 mhz, 8 mhz, and 2 mhz. table 2 : minimum/maximum serial bit timing clk out frequency minimum bit period (host synchronous to clk out ) minimum bit period (host asynchronous to clk out ) maxim um bit period 16 mhz 250 ns 3.25 m s 63.9 m s 8 mhz 500 ns 6.5 m s 127 m s 2 mhz 2 m s 26 m s 511 m s interrupt interface the serial communications line to the SH3001 (pin 14, io/int) also serves as the interrupt to the host microcontroller. the polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the ipol_rctune register (r0x11). this pin is asserted for four cycles of clk out , and then returns to the inactive state. the interrupt line is used by the periodic interr upt/wake - up timer to interrupt the host when it reaches its end of count.
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 11 v1.15 www.semtech.co m io/int timing scenarios 1. int disabled, up initiates write access. active high interrupt. ubuddyioout upioout a0 a4 xxx d0 d7 ... combinedio a0 a4 xxx d0 d7 ... ... 2. int active (high), up initiates write access ubuddyioout upioout combinedio xxx state idle pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 idle xxx state if the interrupt did not get cleared, then it will activate again here 4. int disabled, up initiates read access ubuddyioout upioout a0 a4 xxx ... combinedio a0 a4 xxx d0 d7 ... ... state idle pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard2 idle d0 d7 ... p0 p1 p0 p1 p0 p1 p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 a0 a4 xxx d0 d7 ... a0 a4 xxx d0 d7 ... ... xxx pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 xxx p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 ack0 ack1 guard2 guard3 guard2 guard3 pendin g-start in t idle pendin g-start in t 3. int active (low), up initiates write access ubuddyioout upioout combinedio state if the interrupt did not get cleared, then it will activate again here a0 a4 xxx d0 d7 ... a0 a4 xxx d0 d7 ... ... xxx pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 xxx p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 guard2 guard3 pendin g-start in t idle pendin g-start in t ack0 ack1 rw0 rw1 rw2 guard3 figure 4: serial communication timing diagram
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 12 v1.15 www.semtech.co m note: the SH3001 is esd - sensitive. descrip tion symbol min max units supply voltages on v dd or v bak relative to ground v dd - 0.5 5.5 v input voltage on clk in , io/i nt , test v in 1 - 0.5 v dd + 0.5 v input voltage on clk sel v in 2 - 0.5 v reg + 0.5 v input current on any pin except v reg i in 1 10 ma input current on v reg i in 2 150 ma ambient operating temperature t op - 40 85 o c storage temperature t stg - 55 160 o c ir reflow temperature, (soldering for 10 seconds, tr option) t irrt 240 o c ir reflow temperature, (soldering for 10 seconds, trt option) t irrt 260 o c operating characteristics parameter symbol min typ max units notes case temperature t op ? 40 +85 c supply voltage v dd 2.3 5.5 v supply current, clk out = 16 mhz* i dd 3 ma supply current, clk out = 8 mhz* i dd 1.8 ma supply current, clk out = 2 mhz* i dd 0.9 ma standby current, 32.768 khz crystal** i sb 8 m a clk32 disabled backup supply voltage** v bak 2.3 5.5 v backup current, 32.768 khz crystal** i bup 2 m a clk32 disabled backup standby current** i bsb 50 na v dd > v bo *n ote: assuming load on clk out < 20 pf **note: assuming temperature < 60 o c electrical specifications absolute maximum ratings
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 13 v1.15 www.semtech.co m operating characteristics with crystal oscillator parameter symbol min typ max units crystal operating frequency fop 32.768 khz clk32 duty cycle dc 25 75 % startup time tst 3 secs minimum x in /x out padding capacitance cmin 10 pf maximum x in /x out padding capacitance cmax 40 pf padding capacitance resolution cres 2 pf x in switching threshold vth 0.6 v x in to clk32 delay td 0.5 s clk32 frequency stability (cry stal - dependent) fs 1 ppm/c clk32 cycle to cycle jitter j 0.05 clk32 rise/fall time (10 pf load) trf 10 ns clk32 logic output low (0.5 ma load) vol 0.25 0.5 v clk32 logic output high (0.5 ma load) voh - 0.5 - 0.25 ref v dd * *note: v dd here is v dd during normal operation and v bak during battery backup. operating characteristics of the high - frequency oscillator (hfo) parameter symbol min typ max units minimum operating frequency (start - up default = 2 mhz) fmin 5.6 8 mhz maximum operating fre quency fmax 16.8 21 mhz frequency resolution fres 2 khz programmed frequency accuracy at 25c fst - 0.3 +0.3 % frequency drift over temperature and supply fdrift 0.5 % clk out cycle to cycle jitter (spread spectrum off) j 0.1 % startup time fro m standby tstart 2 s settling time to 0.1% after hf digitally - controlled oscillator (dco) code change tsett 10 s clk out duty cycle dc 40 60 % frequency temperature stability fts 100 ppm/c short term frequency stability fs 0.5 %/sec minimum spread spectrum range ssmin 32 khz maximum spread spectrum range ssmax 256 khz clk out rise/fall time (20 pf load) trf 3 ns clk out logic output low (4 ma load) vol 0.25 0.4 v clk out logic output high (4 ma load) voh - 0.4 - 0.25 ref v dd
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SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 19 v1.15 www.semtech.co m package outline drawing mlp 3 x 3 mm 16 pins
SH3001 micro budd y ? system management copyright ?2002 - 2005 semtech corporation 20 v1.15 www.semtech.co m for sales information and product literature, contact: semtech corporation human interface device (hid) and system management division 200 flynn road camarillo, ca 93012 - 8790 sales@semtech.com http://www.semtech.com/ (805)498 - 2111 telephone (805)498 - 3804 fax copyright ?2002 - 2003 semtech corporation. all rights reserved. semtech, the semtech logo, microbuddy, buddy, and b are marks of semtech corporation. all other marks belong to their respective owners. limited license granted: no warranties made this specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherw ise arising out of any proposal, specification or sample. any suggestions or comments by semtech concerning use of this product are opinion only, and semtech makes no warranty as to results to be obtained in any specific application. a license is hereby granted to reproduce and distribute this specification for internal use only. no other license, expressed or implied to any other intellectual property rights is granted or intended hereby. authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights.

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